The CDC 3000 series computers from Control Data Corporation were mid-1960s follow-ons to the CDC 1604 and CDC 924 systems. Over time, a range of machines were produced - divided into the 'upper 3000 series' and the 'lower 3000 series'. CDC phased out production of the 3000 series in the early 1970s. The 3000 series were the 'cash cows' of Control Data during the 1960s; sales of these machines funded the company while the 6000 series was designed.
The upper 3000 series used a 48 bit word size. The first machine to be produced was the CDC 3600; first delivered in June 1963. First deliveries of the CDC 3400 and CDC 3800 were in December 1965. These machines were designed for scientific computing applications, however were eventually overshadowed by the 60-bit CDC 6000 series machines.
The lower 3000 series used a 24 bit word size. They were based on the earlier CDC 924 - a 24-bit version of the CDC 1604. The first lower 3000 to be released was the CDC 3200 (May 1964), followed by the smaller CDC 3100 (February 1965), and the CDC 3300 (December 1965). The final machine in the series, the CDC 3500, was released in march 1967 and used integrated circuits instead of discrete components. The 3300 and 3500 had optional relocation capabilities, floating point, and BDP (Business + Data Processing) instructions. These machines were targeted towards 'business and commercial' computing.
The instruction set of the upper 3000 series was composed mostly of 24-bit instructions (packed 2 per word), but also contained some 48-bit instructions. The lower 3000 was based on a 24-bit subset of those available on the upper 3000 systems. It was therefore possible to write programs which would run on all 3000 systems. And as these systems were based on the prior 1604 and 924 instruction sets, some backward compatibility also existed. However the systems did diverge from each other in areas such as relocation and the BDP instructions.
Almost all 3000 series computers used core memory. However, the CDC 3500 machine used an integrated circuit memory.
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The lower 3000 CPU was a 24-bit architecture: instructions were 24 bits in length, as were the two operand registers A and Q. There were 4 index registers of 15 bits, B0 through B3, though B0 is always zero (zero when read; writes don't affect the value). There was no status (flags or condition code) register. Up to 32,768 (24-bit) words of core memory could be directly addressed, and multiple banks could be switched in. Two or three memory bank configurations were the most common.
Each instruction contained 6 bits of opcode, 1 bit specifying whether indirect addressing used, 2 bits of index register address and 15 bits of address.
Arithmetic was ones' complement, so there were two forms of zero: positive zero and negative zero. The A and Q register could function as a combined 48-bit register for certain arithmetic instructions. The E register had 48 bits.
The 3300 CPU could execute around 1 million instructions per second (1 MIP), giving it supercomputer status in 1965.
The earliest operating system for the lower 3000 series was called RTS OS. However it was quickly replaced with MSOS (Mass Storage OS). The premier operating system for the CDC 3300 and CDC 3500 was called MASTER. MASTER was interrupt-driven, supported large memory, multi-tasking.
An operating system called REAL-TIME SCOPE existed for both lower- and upper-3000 systems. A disk-based version of SCOPE was eventually made available for the upper-3000 systems.
FORTRAN, COBOL, and ALGOL were available. The assembly language was called COMPASS. These were available from CDC.
An APL system for the upper 3000 series computers was developed at the University of Massachusetts. This system was made available to other users of the upper 3000 series.
The operating systems for the CDC 3xxx typically used 6 bit characters, so the 64 character set did not contain lowercase letters. The character set contained (in display code order). This 6-bit extension of the 4-bit BCD encoding was referred to as BCDIC (BCD interchange code.) IBM later extended this code further to create the 8-bit "extended BCDIC", or EBCDIC code.
: A-Z 0-9 + - * / ( ) $ = (space) , . # [ ] % " _ ! & ' ? < > @ \ ^ ;
Depending on the device, some characters are rendered differently, especially the lineprinter and some terminals:
| character | sometimes displays as |
| # | ≡ |
| " | ≠ |
| _ | → or { |
| ! | ∨ |
| & | ∧ |
| ' | ↑ |
| ? | ↓ or } |
| @ | ≤ |
| \ | ≥ |
| ^ | ¬ |
Note the absence of control characters, especially carriage return and line feed. These were encoded by the record structure.
Oregon State University offered a CDC 3300 for use from the mid to late 1960s up until about 1980. It used a home grown operating system known as OS3 (for Oregon State Open Shop Operating System).
The U.S. Internal Revenue Service used CDC 3000 series computers for many years.
A number of CDC 3000s were installed in France, either in academic computing centers, in software companies or in the aeronautics, nuclear and oil industries.
Communist-ruled Hungary obtained a CDC 3300 machine between 1969 and 1971. It was administered by the National Academy of Sciences throughout the 1970s, mainly for running scientific computations.
International Timesharing Corporation sold timesharing services using a CDC 3600.
California State University at Northridge had a dual 3170 that provided timesharing service to the California State University and College system. Many of the other campuses also had CDC 3150 machines for local batch operation.
The US Force used numerous CDC 3800 series systems in the AFSCF Air Force Satellite Control Facility located at what is now Onizuka Air Force Station in Sunnyvale CA. As part of the Air Force Satellite Control Network they were used to do orbital planning and maintenance calculations for DOD satellites until they were phased out and replaced by IBM mainframes in the mid 1980s. These systems used the JOVIAL programming language to provide the accuracy necessary for these calculations.
Other CDC 3300 systems installed in former Eastern Bloc Countries (list not complete):